The present invention relates to a semiconductor device and a semiconductor chip.
In a semiconductor chip, electrode pads connected with an internal circuit are generally provided along the edge of the semiconductor chip. A technology has been known in which bumps are provided on the electrode pads and electrically connected with an interconnect pattern of a substrate in a state in which the bumps face the substrate (JP-A-9-237800, for example).
In recent years, the area of the electrode pad has been reduced along with a reduction in size of the semiconductor chip. Therefore, the size of the bump is also reduced, whereby the area of the mounting surface is decreased. A decrease in the area of the mounting surface may impair reliable electrical connection with the interconnect pattern of the substrate. Moreover, when inspecting the electrical characteristics of the semiconductor chip using the bump, inspection efficiency may be decreased due to the small contact surface with an inspection terminal.